1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a dynamic semiconductor memory device operable in a self-refresh mode for internally and periodically refreshing data of memory cells. More particularly, the invention relates to a structure for reducing a current consumption of the semiconductor memory device immediately after supply of a power, i.e., power-on.
2. Description of the Background Art
FIG. 23 schematically shows a whole structure of a conventional dynamic semiconductor memory device. In FIG. 23, the conventional semiconductor memory device includes a memory cell array 1 having a plurality of memory cells MC arranged in a matrix form, an address buffer 2 for taking in an externally supplied address signal Ad and producing an internal row address signal and an internal column address signal, a row select circuit 4 which decodes the internal row address signal from the address buffer 2 when activated, and drives a corresponding row in the memory cell array 1 to the selected state in accordance with the result of decoding, a sense amplifier band 6 which senses, amplifies and latches data of the memory cell columns (bit line pairs BL and /BL) in memory cell array 1 when activated, and a column select circuit 8 which decodes the column address signal from address buffer 2 when activated, and selects an addressed column in the memory cell array 1 for connecting the same to an internal data bus.
In memory cell array 1, word lines WL are arranged corresponding to the rows of memory cells, respectively, and bit line pairs BL and /BL are arranged corresponding to the columns of memory cells, respectively. FIG. 23 representatively shows one word line WL and one bit line BL. Memory cell MC includes a capacitor C for storing information, and an access transistor T which connects capacitor C to corresponding bit line BL (or bit line /BL) when the corresponding word line is selected.
Row select circuit 4 includes a row decode circuit which decodes the internal row address signal from address buffer 2, and a word line drive circuit for driving word line WL, which is arranged corresponding to the row addressed in accordance with the output signal of the row decoder circuit, to the selected state.
Sense amplifier band 6 includes sense amplifier circuits which are arranged corresponding to the bit line pairs, respectively. Generally, bit lines BL and /BL during standby are precharged, e.g., to an intermediate voltage level, and data of the memory cell is read onto one of paired bit lines BL and /BL in an active cycle. The sense amplifier circuit differentially amplifies and latches potentials on a corresponding bit line pair.
Column select circuit 8 includes a column decode circuit which decodes the internal column address signal from address buffer 2, and an I/O gate which connects a corresponding column in memory cell array 1 to an internal data line in accordance with the column select signal from the column decode circuit.
The semiconductor memory device further includes an internal control signal generating circuit 10 which generates required internal control signals in accordance with externally applied row address strobe signal /RAS, column address strobe signal /CAS and write enable signal /WE, and an I/O (input/output) circuit 12 which performs external input/output of data to and from the memory cell selected by column select circuit 8 under the control of internal control signal generating circuit 10.
Row address strobe signal /RAS is a signal defining a memory cycle, and more specifically defines a standby cycle and an active cycle. When this row address strobe signal /RAS is activated to attain L-level, the semiconductor memory device starts the memory cell selection operation. Column address strobe signal /CAS is a signal providing a start timing of the column selection operation. Write enable signal /WE is a signal designating data write/read modes. The timing of data reading is determined by column address strobe signal /CAS, and the timing of writing data into the selected memory cell is determined by activation of both column address strobe signal /CAS and write enable signal /WE. Now, an operation of the semiconductor memory device shown in FIG. 23 will be described below with reference to an operation waveform diagram of FIG. 24.
When row address strobe signal /RAS is at H-level, this semiconductor memory device is in a standby cycle, and each of internal circuits has been precharged. In this standby cycle, precharged potential levels of the internal circuits are predetermined.
When row address strobe signal /RAS falls to L-level, the active cycle starts, and the memory cell selection operation starts. In response to this falling of row address strobe signal /RAS, address buffer 2 takes in externally applied address signal Ad, and forms the internal row address signal for applying the same to row select circuit 4. Row select circuit 4 drives the word line, which corresponds to an addressed row in memory cell array 1, to the selected state in accordance with the applied internal row address signal. The potential on word line WL thus selected rises to H-level. In memory cell MC connected to the selected word line WL, access transistor T is turned on, and charges stored in capacitor C are read onto corresponding bit line BL or /BL. The other of paired bit lines holds the precharged potential level. FIG. 24 shows potential variations on bit lines BL and /BL in the case where data at L-level is stored in the memory cell. When the word line is driven to the selected state, and the potential difference on the bit line pair increases, sense amplifier band 6 is activated, and the potentials on each bit line pair are differentially amplified and latched.
When column address strobe signal /CAS falls from H-level to L-level, address buffer 2 produces and applies the internal column address signal to column select circuit 8 in accordance with externally applied address signal Ad. Column select circuit 8 selects a bit line pair corresponding to the column thus addressed, and connects the same to the internal data bus. When I/O circuit 12 is in the read mode, data of the memory cell on the column selected by column select circuit 8 is output as output data Q.
When one memory cycle is completed, row address strobe signal /RAS and column address strobe signal /CAS rise to H-level, and the internal circuits return to predetermined initial states, respectively. Thus, the potential level of selected word line WL lowers to ground potential level achieving the nonselected state, and bit lines BL and /BL are precharged to the predetermined intermediate potential level.
In the dynamic semiconductor memory device, as described above, the active cycle starts in such a state that internal signal lines and nodes are already precharged to predetermined potential levels, respectively. In a normal operation mode, row address strobe signal /RAS is lowered to L-level, and thereafter column address strobe signal /CAS is lowered to L-level. When column address strobe signal /CAS is lowered to L-level prior to lowering of row address strobe signal /RAS, a special mode such as a self-refresh mode is executed as will be described later.
FIG. 25 schematically shows a structure of a portion related to row address strobe signal /RAS and contained in internal control signal generating circuit 10 shown in FIG. 23. In FIG. 25, internal control signal generating circuit 10 includes an RAS buffer 10a which receives row address strobe signal /RAS and a power-on detection signal /POR, and generates the internal row address strobe signal in accordance with row address strobe signal /RAS when power-on detection signal /POR is active (H-level), and an RAS-related control circuit 10b which generates control signals for controlling operation of circuit portions (i.e., RAS-related circuits) related to row address strobe signal /RAS in accordance with the internal row address strobe signal from RAS buffer 10a.
RAS buffer 10a includes a gate circuit 10aa which drives the internal row address strobe signal to the active state of L-level when power-on detection signal /POR is in the active state of H-level and row address strobe signal /RAS is at L-level. Power-on detection signal /POR attains the active state of H-level when an externally applied power supply voltage is stabilized at a predetermined voltage level or a steady state.
RAS-related control circuit 10b generates control signals for controlling circuit portions related to row address strobe signal /RAS, i.e., circuits in portions related to the row selection. FIG. 25 representatively shows a row address latch instructing signal RAL for latching, as a row address signal, an external address signal applied to the row address buffer, a word line drive signal RX for providing a timing at which a selected word line is driven to the selected state in the memory cell array, and a sense amplifier activating signal SA for activating the sense amplifier band.
RAS-related control circuit 10b further generates other signals such as a bit line equalize/precharge signal for precharging/equalizing the bit lines to a predetermined potential, and a row decoder enable signal for activating the row decoder included in the row select circuit. Under the control of RAS-related control circuit 10b, row select circuit 4 and sense amplifier band 6 operate to perform operations including sensing, amplification and latching of data of memory cells connected to the selected word line when the internal row address strobe signal is active. Operations of the internal control signal generating circuit shown in FIG. 25 will be described below with reference to FIGS. 26 and 27.
Referring first to FIG. 26, description will now be given on the operation performed when the semiconductor memory device is powered on while row address strobe signal /RAS is at H-level. At time t1, row address strobe signal /RAS is at H-level, and the power is turned on, so that a potential level of an external power supply voltage EXTVcc rises. At the time of power-on, power-on detection signal /POR is still at L-level, and the internal row address strobe signal from RAS buffer 10a is at H-level.
In this state, each of the internal circuits in the semiconductor memory device is set to the initial state, and a slightly large current Ic is consumed for precharging each internal signal line to the initial state. After each of the internal signal lines and internal nodes is set to the initial state, each internal signal line is driven to a predetermined potential level in accordance with rising of the potential level of external power supply voltage EXTVcc. In this state, only a small standby current flows.
At time t2, external power supply voltage EXTVcc reaches a predetermined voltage level (or reaches the steady state at a predetermined voltage level), and responsively power-on detection signal /POR attains H-level. In RAS buffer 10a, row address strobe signal /RAS is at H-level, and therefore internal row address strobe signal from gate circuit 10aa is in the inactive state of H-level, and the internal circuits maintain the standby state.
At time t3, row address strobe signal /RAS is lowered to L-level for performing, e.g., a dummy cycle. Thereby, internal row address strobe signal from RAS buffer 10a lowers to L-level, and a control signal from RAS-related control circuit 10b is driven to the active state. In FIG. 26, an RAS-related control signal .phi.RAS is representatively shown as a signal for controlling the RAS-related circuits related to row address strobe signal /RAS. In accordance with activation of RAS-related control signal .phi.RAS, an internal circuit operates and a large current Ic flows, and sense amplifier band 6 (see FIG. 23) operates to sense and amplify memory cell data. Thereafter, current Ic is stabilized at a constant current level.
Therefore, when the semiconductor memory device is powered on in such a state that externally applied row address strobe signal /RAS is set to H-level under control of a memory controller, each internal node can be precharged with a low current consumption with the internal circuit maintained at the initial state.
Power-on detection signal /POR is supplied only to RAS buffer 10a. A CAS buffer receiving column address strobe signal /CAS is not supplied with power-on detection signal /POR. This is because activation of the internal column address strobe signal is performed after activation of the internal row address strobe signal.
When the semiconductor memory device is powered on with row address strobe signal /RAS set at H-level, in the semiconductor memory device, the internal row address strobe signal from the RAS buffer is inactive, and the internal circuits are supplied with current while maintaining the standby state, and are set to the initial state. Therefore, the current supply amount at the time of power-on slightly increases only immediately after power-on, and can be sufficiently small. Generally, a current flowing through the semiconductor memory device on standby is tens of microamperes to several microamperes.
However, there are some cases in which the memory controller may malfunction, e.g., during rise-up of the system power, and a power is supplied to the semiconductor memory device with row address strobe signal /RAS being at L-level. This state will be described below with reference to FIG. 27.
At time t1, row address strobe signal /RAS is at L-level, and the device is powered on. At time t1, the voltage level of external power supply voltage EXTVcc starts to rise. At this time, power-on detection signal /POR is still at L-level, the internal row address strobe signal from RAS buffer 10a is inactive, and the internal circuits in standby state are supplied with a current and internal nodes and signal lines are precharged to a predetermined potential. During this period, therefore, a slightly large current flows for charging the internal signal lines and internal nodes at time t1, i.e., only at the time of power-on, and the steady state is subsequently attained, so that the internal signal lines and internal nodes are precharged to the predetermined potentials, respectively.
At time t2, external power supply voltage EXTVcc reaches the predetermined voltage level or is stabilized at the constant voltage level, and power-on detection signal /POR rises to H-level. In response to rising of power-on detection signal /POR, the internal row address strobe signal from gate circuit 10aa attains L-level, and RAS-related control circuit 10b is activated. Thereby, RAS-related control signal .phi.RAS is activated, and the internal circuit operates, so that a large current flows. Subsequently, the sense amplifier completes its operation, and stabilization is attained with a relatively large current flowing.
When the power is turned on with row address strobe signal /RAS set at L-level, the internal circuit operates in response to rising of power-on detection signal /POR, and a large operation current flows. Then, a stabilized state of the internal circuit is attained with a relatively large current flowing. This results in disadvantageous increase in current consumption immediately after power-on.